The present disclosure relates to fabrication of integrated circuits, semiconductor devices and other miniaturized devices, and more particularly, to fabrication of three-dimensional integrated circuits (3D-ICs) including semiconductor dies encapsulated in an oxide bonded wafer stack.
As semiconductor device sizes have decreased, 3D device integration has become a desired method for increasing the density of integrated circuits and/or semiconductor devices, offering much smaller form factor along with higher performance and lower power compared to 2D designs. 3D-IC assemblies are comprised of two or more stacked layers of active electronic components (e.g., sensors and readout circuits) using horizontal intra-tier and vertical (through-silicon vias, TSVs) inter-tier connectivity so that they behave as a single device. Package-to-package stacking and die-to-die (D2D) stacking allow selection of “known good dies” for stacking and can provide higher yield but limited performance improvement compared to 3D. 2D approaches sometimes use wire bonds that require a long connection which slows the speed and limits the number of possible connections. More elegant 2.5D solutions use bump bonds to an interposer that provides routing between circuits, but still result in higher power and lower performance than true 3D circuits. Also, due to the ultra-thin nature of the die, D2D stacks are difficult to handle and susceptible to breakage and contamination. Wafer-to-wafer (W2 W) 3D stacking allows TSVs to be scaled down to smaller diameters with thinner wafers permitting higher 3D connection densities leading to higher bandwidth, performance, and power improvements and offering lower manufacturing costs. However, 3D stacking can suffer from reduced yields since, if any one of N chips in a 3D-IC is defective, the entire 3D-IC will be defective. In addition, the wafer stacking is optimal with wafers of the same size, and since non-silicon materials (e.g., III-V's) are typically manufactured on smaller wafers than silicon CMOS logic or DRAM, wafer level heterogeneous integration can pose manufacturing and yield challenges.
3D integration using oxide bonding has been primarily used to bond full wafers as the processing is not as mature for bonding at the die level. Solder-seal wafer level packaging has been demonstrated, as has bonding of wafers with cavities. Known techniques are available for direct metal to metal bonding of an integrated circuit die onto a silicon wafer, but the techniques have limitations for high layer count wafer stacking die to process stress, yield, interconnect density and thermal limitations. Other techniques have integrated multiple die onto an interposer, but have neither extended the stacking further in the z-axis to more than 2-3 layers, nor achieved heterogeneous or hermetically sealed devices.
The present disclosure contemplates a new and improved method for fabrication of 3D-ICs using die encapsulation that overcomes current limitations. Some embodiments also address the needed for on-chip thermal management permitting higher power dissipation and greater packaging densities.